Daily Archives: September 25, 2018

Reverse Engineering PCIE Backplane Gerber File

The detail plan of this level consume only 30 seconds to complete the task, once this plan has been obtained, the engineer will probably want to Reverse Engineering PCIE Backplane Gerber File or create the topology plan for next layer immediately, and then use automatically layout to finish all of the topology plan.   From…

Server Backplane Board Reverse Engineering

Accompany with the DATA-BUS being organized into the tight trace by tissue on the first layer, designer start to plan the detail #3 to the 3rd layer’s conversion. And considering the matching distance of the Server Backplane Board, please notice, this topology route on the 3rd layer must be wider than the top layer, and…